Lauro Rizzatti Build testability into a custom chip during the design phase Source: Electronic Product Of all the electronic design automation (EDA) tools on the market, design for test (DFT) may be the most under-appreciated; even though building testability into a chip during the design phase will significantly lower hefty testing costs. According to recent analysis, the … Read more
Source: EDACafé The 2016 DVCon Europe was held in Munich, Germany, at the Holiday Inns City Center Hotel on October 19-20. This was the third year of the conference and it has a decidedly local focus. In its short life, DVCon Europe has become the leading European event for electronic industry participants, mainly chip and … Read more
By using the well-tested Gompertz function, semiconductor companies have a way to determine areas in which to focus their attention and investments. Source: EETimes Is there a way to predict the future of semiconductor revenue driven by new products? This was the provocative question Dr. Walden (Wally) Rhines, Chairman and CEO of Mentor Graphics, asked and … Read more
This transcript of a panel discussion that took place at DVCon India is chock-full of interesting information and invaluable advice Source: EETimes At DVCon India in September 2016, I moderated a panel titled The Future Verification Flow. Joining me were Ashish Kumar, senior engineering manager at Broadcom India, and Shankar Bhat, verification and validation director at Qualcomm … Read more
Source: EDACafé In its third year, DVCon India 2016 was held in Bangalore September 15-16, hosted in the Leela Palace, as it was in 2015, an island of serenity, peace and comfort in the center of Bangalore. Although I don’t want to repeat myself, my 2015 report included my assessment that “the traffic on Bangalore’s roads … Read more
In 2010, digital data storage requirements hit the “Zetta” prefix, with only one prefix, the “Yotta,” left available Source: EETimes Until the 19th century — let’s say until the Napoleonic Wars — life on earth proceeded at a slow pace with no significant differences over long periods of time. If you were a farmer in ancient … Read more
Source: EDACafé DVCon India could be considered the official start of the fall season for our industry. It kicks off Thursday, September 15, and runs through Friday, September 16, at The Leela Palace in Bangalore, an elegant hotel and a great place to host a content-rich technical event like this. The two-day event, now in its … Read more
Source: EDACafé I had a chat with a friend yesterday who announced: “Less efforting is working for me.” The use of the noun effort as a verb –– efforting –– didn’t send me to my online dictionary to check my grammar or linguistic skills. Instead, it took me back 30-odd years to the early days of … Read more
Source: EDACafé A panel in DAC’s technical program this year continues to yield returns. I looked over my notes the other day and found that the moderator and the five panelists identified a few trends that are outside the scope of the traditional verification as known for many years. Trend #1: Engineering and verification teams are … Read more
Source: FormalWorld DAC attendees this year were treated to an informative panel moderated by Adapt-IP’s John Sanguinetti titled, “The Great Simulation/Emulation Faceoff,” a lively debate about whether the simulation/formal verification flow works more effectively than a simulation/emulation flow. Panelists were Stephen Bailey of Mentor Graphics, Dave Kelf from OneSpin, IBM’s Ronny Morad, Frank Schirrmeister at Cadence … Read more