Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive Despite abundant rumors predicting the end of life for Moore’s Law (the axiom stating transistor density doubles every 24 months), semiconductor design sizes continue to grow exponentially with no end in sight. In the process, design sizes push costs off the roof. According to market research International Business Strategies (IBS), the total cost of … Read more

What’s Behind Hardware Emulation’s Rising Status? Five common questions often come up when chip designers and verification engineers ask me about hardware emulation. All are well-considered and answers are widely shared. Today, emulation is mandatory in the design verification toolbox. Why? For two unrelated reasons: the ever-increasing demand for performance and throughput from verification tools and the remarkable progress in … Read more

Chip Design Challenges: Driving the Need for Hardware-Assisted Verification In the span of a few short months earlier this year, Mentor Graphics became Siemens EDA and introduced a suite of integrated hardware-assisted verification tools, the first product launch under the new Siemens EDA brand. Jean-Marie Brunet, senior director of marketing, product management and product engineering at Siemens EDA, orchestrated the launch and connected … Read more

All for One, One for All: An Enterprising Tale of Hardware SoC Verification

In summary: Emulators provide the capacity and debug visibility needed for verifying large SoCs, including hardware, software drivers, operating systems, and portions of application code. Enterprise FPGA prototypes provide higher-performance hardware for running emulation regression suites, executing ICE tests, and verifying application software. Desktop FPGA prototypes are available to software developers who want more direct contact with their … Read more

Hardware Emulation Embraces Machine Learning Editor’s note: Two years ago, Lauro Rizzatti talked with Thomas Delaye, product engineering director at Siemens EDA, about applying machine learning to hardware emulation. (See: Can AI Help Manage the Data Needed for SoC Verification?) Rizzatti recently asked Delaye for an update. What follows is a condensed version of their conversation. Lauro Rizzatti: Fast forward, … Read more

Hardware-Assisted Verification Through the Years

A quick glance in today’s design verification toolbox reveals a variety of point tools supporting the latest system-on-chip (SoC) design development. When combined and reinforced by effective verification methodologies, these tools trace even the most hard-to-find bug, whether in software or in hardware. The focus on tools and delivering a tightly woven integration between complementary … Read more

Smoothing the Wrinkles of Chip Design Verification and Validation

If chip design had a face, it would have a wrinkle or two, an especially deep one caused by the increasingly complex challenge of hardware and software verification. Until recently, these two elements of a system design were done separately and at different times, with hardware design often beginning way ahead of software development. Generic … Read more

11 Myths About Hardware-Assisted Verification

Verification expert Dr. Lauro Rizzatti debunks the myths surrounding the two tool classes of HAV platforms—hardware emulators and FPGA prototypes. What you’ll learn: What are hardware emulators and FPGA prototypes? Who are the main players in this market? What are the two modes that HAV platforms operate in, and which is preferable? Editor’s Note: Following the … Read more

Market-Driven Trends in Hardware Emulation

Five of the largest semiconductor vertical markets are combining to drive several of the widest industry trends: unending growth in design complexity and size, proliferation of peripherals, increase in computing power, surging I/O traffic activity, and a critical need to contain the otherwise escalating energy consumption. The cumulative effects of these trends impact dramatically the design … Read more