Articles Authored by Lauro Rizzatti

In a recent talk on deep learning, BabbleLabs CEO Chris Rowen said, “I think of it as the construction of a complex numerical model that mimics the behavior of an even more complex but hidden system. The hidden system in question is often the brain.”

Silicon system design with deep learning has the same challenges with other complex system-on-chip-based designs, only more so.

Changes to 2020 SSD controllers versus 2018 SSD controllers are comparable to the task of migrating from HDD controllers to SSD controllers.

Combining these Apps with an emulation environment makes it possible to increase fault coverage, increase production yield, and reduce ATE test time and cost.

Mipsology’s Zebra Deep Learning inference engine is designed to be fast, painless, and adaptable, outclassing CPU, GPU, and ASIC competitors.

A more efficient flow to support DSP development groups, such as VSORA’s, could help to ensure the success of 5G.

There are challenges unique to designing ASICs for networking applications. One is that bandwidth and latency performance tests for these devices require significantly more simulation cycles than required by other types of ICs.

Reading the transcriptions and watching the videos of these three talks delivers an exhilarating look at the semiconductor industry’s future.

This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.

Challenges facing chip design verification engineers are plentiful, but the opportunities, especially for AI applications, are abundant.