Articles Authored by Lauro Rizzatti

If chip design had a face, it would have a wrinkle or two, an especially deep one caused by the increasingly complex challenge of hardware and software verification.

Verification expert Dr. Lauro Rizzatti debunks the myths surrounding the two tool classes of HAV platforms—hardware emulators and FPGA prototypes.

Five of the largest semiconductor vertical markets are combining to drive several of the widest industry trends: unending growth in design complexity and size, proliferation of peripherals, increase in computing power, surging I/O traffic activity, and a critical need to contain the otherwise escalating energy consumption.

The 35-year-old field programmable gate array (FPGA) is one of the most impressive semiconductor devices ever created, short of the central processing unit (CPU). Today, it is more popular than ever before, reinvigorated by its intrinsic raw processing power and adaptability, a perfect match for accommodating the rapid evolution of the electronic industry.

Siemens EDA recently introduced a comprehensive hardware-assisted verification system comprised of hardware, software and system verification that streamlines and optimizes verification cycles while helping reduce verification cost.

A unified virtual-prototyping environment allows verification to progress with models early, gradually building the system as different pieces emerge from development, breaking dependencies between hardware design groups and software developers.

Chip design verification is a persistent obstacle that often prevents on-time product delivery. A unified software-enabled verification and validation environment could be the way to break dependencies between hardware design groups and software developers.

In this interview with Ravi Subramanian, he identifies the latest semiconductor trends, as well as what’s driving those trends, how they are affecting chip design and functional verification and why he is bullish on hardware-assisted verification.

A quick glance in today’s design verification toolbox reveals a variety of point tools supporting the latest system-on-chip (SoC) design development. Combined and reinforced by effective verification methodologies, these tools trace even the most hard-to-find bug, whether in software or in the target hardware.

Due to the switch from planar CMOS to FinFET technology, accurate pre-silicon power estimation is more important than ever for system-on-chip designs.