Lauro Rizzatti Source: Kilopass The recent announcement from a large electronic design automation (EDA) vendor touting its hardware emulation tools’ expanded support for system-level memory designs is welcome news. Hardly surprising, though, given the massive amount of verification horsepower needed to analyze and debug today’s memory-filled SoC designs. From what I can glean from the company’s marketing materials, … Read more
We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug Source: Tech Design Forum More than 90% of all system-on-chip (SoC) designs contain embedded processors that must be tested in the context of the final design before silicon is available. You cannot … Read more
Hardware emulation has become a key component of a project team’s verification strategy, used to effectively debug complex system-on-chip (SoC) designs Source: Electronic Design Lauro Rizzatti is more than one of our longest-running Contributing Technical Experts. He also was general manager of EVE-USA and its vice president of marketing before Synopsys acquired it. He also is a global citizen, whose 30-year … Read more
Emulation allows the register transfer level (RTL) source code to be used as the model but with enough processing performance to enable system-level work, especially when it involves software development or running software workloads. Source: Electronic Design More design is being done at the system level than ever before. The enabling technology for much of it … Read more
If loaded with enough resources, a modern emulator can be accessed 24/7 and shared among tens of concurrent users distributed on a vast territory covering multiple continents. Source: EETimes A light breeze was clearing the starry sky in Bangalore, India, on a warm early spring Friday evening. Down on earth, the weekend rush hour made the … Read more
Source: Chip Design These days, you’d need to be buried under a pile of verification reports not to know that hardware emulation has gone mainstream, moving away from a dusty back room to your cubemate’s desktop. The metamorphosis did not happen overnight –– it was more like a decade-long journey –– but once it happened, the … Read more
The number of times the word emulation was uttered: 35 for Mentor, 21 for Cadence, three for Synopsys… Source: EETimes Hardware emulation has become a mainstay of most verification strategies. Why, then, has conventional wisdom held that the hardware emulation market will never rise beyond $300 million in revenue and has a limited future growth? It … Read more
The forthcoming Design Automation Conference (DAC) will be a prime venue to learn more about the varied uses of hardware emulation. Source: EETimes As much as I would like to take credit for the title of this viewpoint, I must step back and give credit to D.A. Davidson, a financial analyst firm that follows the Electronic … Read more
Source: EDA Café It wasn’t all that long ago when hardware emulation providers heading to DAC worked overtime to get their booths filled with interested verification engineers with big challenges. Hardware emulation was still viewed as an esoteric and expensive luxury that only few could afford. Fast forward to 2014. This year is prime time for … Read more
The fundamental difference between commercial FPGA-based emulators and emulators based on custom silicon lies in the core element that maps the design-under-test (DUT) Source: Electronic Design For more than 10 years, I was a vocal advocate of FPGA-based emulation systems and continued to tout their benefits through 2013.1 Since then, I’ve become a consultant with an expertise … Read more