2015

Misconceptions and outright falsehoods can skew the perception of hardware emulation.

One day recently, I was considering the varied use models for hardware emulation.

Risk aversion, which comes from the uncertainty associated with committing a design to silicon, is the name of the game.

The 2015 DVCon/Europe was held in Munich at the Holliday Inns City Center Hotel November 11-12.

At the beginning of the third decade, circa 2005, system and chip engineers were developing evermore complex designs that mixed many interconnected blocks, embedded multicore processors, digital signal processors (DSPs) and a plethora of peripherals, supported by large memories.

The 2015 DVCon/Europe was held in Munich at the Holliday Inns City Center Hotel November 11-12.

Graphics chips, the longtime champs of massive designs, have lost their title to the new heavyweight, Ethernet switch and router chips, which weigh in at half a billion or more ASIC-equivalent gates.

Project teams designing complex switches and routers have turned to hardware emulation as the foundation for their verification strategy to battle network congestion and outages.

By preserving capacity without sacrificing coverage, verification engineering teams get comprehensive functional verification with minimal incremental effort and without a hit on emulation capacity.

Recently, I read a quote from Peter G. Davis from The New York Times in 2007, who wrote: “’Cosi` fan tutte’ was virtually unknown a half-century ago, considered a trivial farce scarcely worth reviving.