Graphics chips, the longtime champs of massive designs, have lost their title to the new heavyweight, Ethernet switch and router chips, which weigh in at half a billion or more ASIC-equivalent gates.
The complexity of the networking chip stems from a set of unique characteristics such as large number of ports, expanded throughput, decreased latency, and improved security to assure fewer network failures and collisions when packets are transmitted simultaneously.
Just consider the verification plan of a recent Ethernet switch SoC design with a 128-port interface and a variable bandwidth of 1/10/40/100/120Gbps. The project team decided against using an HDL simulator, the traditional and most popular verification tool.
The design size encompassed several hundred million gates, and required about five hours to compile using a simulator. Even worse, configuring the design in simulation added another 18 hours. Simulation time for one packet of data took two hours. At that rate, a simulation farm with a few hundred PCs would reach a maximum throughput of about 1,000 packets per day, way short of the multi-million packets necessary to debug the design within any realistic time frame.
Instead, the team used hardware emulation in a virtual mode, a new use model that conveniently and efficiently handles multiple users in a datacenter-like scenario. In the virtual approach, the physical target system used to generate and process real data to and from the design-under-test (DUT) is replaced by a functionally equivalent software-based test environment. It performs the same operations at the same speed of an in-circuit emulation (ICE) environment. Known as Ethernet VirtuaLAB, it is a new offering from Mentor Graphics. See news release at: http://bit.ly/1KAPCCd
I should point out that the virtual approach is the next step for hardware emulation and a move away from the long-used ICE mode, a way to test a design with real traffic. The random nature of the real world makes the testing environment in ICE mode rather unpredictable. Bugs show up at different time stamps or not at all in subsequent runs. But, unlike the ICE mode, the virtual mode assures predictability essential to quickly zoom in on a bug by running repeatedly an emulation session.
While ICE has well-served project teams, it’s melting. An ICE configuration needs one Ethernet tester per port. Since a direct connection is not possible due to the different speed domains between the tester and the DUT, a speed rate adapter is inserted between the two to resolve the speed difference.
For this particular design with 128 ports, the ICE setup would need 128 Ethernet testers and 128 Ethernet speed adapters and loads of cables, increasing the setup cost and amplifying the risk of missing the verification schedule.
In the VirtuaLAB the Ethernet testers were modeled in software running under Linux on a workstation connected to the emulator. The model was an accurate representation of the actual physical tester, based on production-proven IP. This virtual tester included an Ethernet Packet Generator and Monitor (EPGM) that generates, transmits and monitors Ethernet packets with the DUT. It can configure GMII, XGMII, XLGMII/CGMII and CXGMII interfaces for 1G, 10G, 40G/100G and 120G respectively. The software performed off-line analysis of the traffic, provided statistics and supported other functions. The interface between the virtual tester and the DUT included one instance of a SystemVerilog interface communicating to a Virtual Ethernet xRTL (extended Register Transfer Level) transactor hooked up to a Null-PHY, connected to the DUT. One xRTL transactor was required for each port of any xMII supported type.
The system is able to provide up to 64 GMII, XGMII, XLGMII/CGMII and CXGMII ports per workstation. Multiple EPGMs can be bundled together across multiple workstations to support large port count configurations. High Speed Link (HSL) cards can be used to connect co-model channels from workstations to the emulator. This allows for configuring a system either for best performance or capacity or usability.
In our case study, the time to compile the design in emulation increased threefold. More important, the emulator configured the design in 10 minutes and processed one packet of data in less than one second. The acceleration was more than 100X to reconfigure the design and close to 10,000X to process data. In one day of emulation, it was possible to execute 11-million packets over 128 ports, mandatory to trace bugs in a reasonable timeframe.
Companies designing networking chips have come to rely on hardware emulation for their verification tasks, especially now that emulation is available to support the network domain in a datacenter-like configuration.