Risk Avoidance, Hardware Emulation Style

Risk aversion, which comes from the uncertainty associated with committing a design to silicon, is the name of the game.

Source: EETimes

December is normally a month in which we take a moment to look back over the preceeding year. With this in mind, I skimmed through the blog posts I’ve written for EE Times in 2015 on one of my favorite topics — hardware emulation. What struck me as an unwritten, but recurring, theme is hardware emulation’s ability to alleviate risk for development teams and project managers.

(Source: pixabay.com)

I can think of an analogy to buying an insurance policy. Such a policy may protect you and your family against the risk of a premature death, a house disaster, a car crash, and other unforeseen calamitous events. Likewise, hardware emulation provides insurance to reduce, or eliminate, costly re-spins. And, even more important, hardware emulation can accelerate time-to-market by delivering thoroughly verified RTL and gate-level designs to the backend design flow, along with validated embedded software ahead of silicon availability. Furthermore, it can perform post-silicon testing to weed out any bugs remaining after tape-out.

“Why and how is all this possible?” you may wonder.

Hardware emulation is the most versatile verification tool ever developed, and now it has gone mainstream. It has the speed, performance, and capacity necessary to tackle even the most complicated debugging scenarios that often include embedded software content. Bugs hiding out in the most complex chips designed today, such processors, graphics engines, or networking switches and routers, have now met their match with hardware emulation.

During a panel session at an industry conference earlier this year, a verification engineer was asked what he used emulation for. His reply: “Everything!” It’s a safe bet he knows that much of the risk associated with debugging a chip has been removed through his hardware emulation resource.

In my travels to India, Europe, and throughout the US this year, I heard many times that hardware emulation is a highly-valued and well-used verification tool. As I wrote in January, its four deployment modes and (at that time) at least eight verification objectives could be why. All of them concur to alleviate risk. No project team wants to chance failure by committing a buggy chip to silicon and enduring an expensive re-spin.

Risk aversion, which comes from the uncertainty associated with committing a design to silicon, is the name of the game. Software developers, hardware designers, and verification engineers have arrived at this conclusion and rely on hardware emulation to debug an SoC design’s hardware and software. It can be used for all types of hardware designs (with the exception of anything analog) ranging in size from one-million to more than one-billion ASIC equivalent gates.

The “Big Three” EDA vendors offer hardware emulators in their product portfolios, each with a distinct architecture to give development teams more options. One vendor chose to employ a processor-based architecture; the second, a custom emulator-on-chip architecture; while the third employs a commercial FPGA-based architecture. All three have gained market acceptance.

These vendors recognize the effectiveness of these powerful machines, and have added new features and improved capabilities in 2015. Dynamic power consumption provides one example. As another, emulation has become a datacenter resource through a transaction-based emulation mode or acceleration mode, a capability that’s met the approval of many development teams.

Long gone are the spaghetti wires running from the emulator box — a risk themselves for lowering the reliability of the system. These days, a hardware emulator is a stylish, sleek box with fewer cables to manage.

I have no doubt that hardware emulation is the way to avoid risk for SoC design debugging. In 2016, you can expect more updates from me from the hardware emulation world, including new capabilities, applications, and even a few case studies. Meanwhile, Happy Holidays!

Dr. Lauro Rizzatti is a verification consultant and industry expert on hardware emulation (www.rizzatti.com). Previously, Dr. Rizzatti held positions in management, product marketing, technical marketing, and engineering. He can be reached at lauro@rizzatti.com.