2014

“Have it your way” seems like just the right strategy to get a chip design verified correctly.

The recent announcement from a large electronic design automation (EDA) vendor touting its hardware emulation tools’ expanded support for system-level memory designs is welcome news.

We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.

Hardware emulation has become a key component of a project team’s verification strategy, used to effectively debug complex system-on-chip (SoC) designs.

If loaded with enough resources, a modern emulator can be accessed 24/7 and shared among tens of concurrent users distributed on a vast territory covering multiple continents.

If loaded with enough resources, a modern emulator can be accessed 24/7 and shared among tens of concurrent users distributed on a vast territory covering multiple continents.

These days, you’d need to be buried under a pile of verification reports not to know that hardware emulation has gone mainstream, moving away from a dusty back room to your cubemate’s desktop.

The forthcoming Design Automation Conference (DAC) will be a prime venue to learn more about the varied uses of hardware emulation.

It wasn’t all that long ago when hardware emulation providers heading to DAC worked overtime to get their booths filled with interested verification engineers with big challenges.

The fundamental difference between commercial FPGA-based emulators and emulators based on custom silicon lies in the core element that maps the design-under-test (DUT).