The recent announcement from a large electronic design automation (EDA) vendor touting its hardware emulation tools’ expanded support for system-level memory designs is welcome news. Hardly surprising, though, given the massive amount of verification horsepower needed to analyze and debug today’s memory-filled SoC designs.
From what I can glean from the company’s marketing materials, its emulation platform will give project teams –– these days, a mix of hardware engineers and software developers –– a way to test their SoC with memory devices integrated on their chip designs. They’re able to develop and stress-test their software and hardware with billions of verification cycles well before silicon availability, shaving time and other resources.
Some readers may be unimpressed because FPGA prototyping handles memory designs and has done so since the 1970s. Let’s see how the two hardware-assisted verification techniques approach memory design.
Hardware emulation is different than FPGA prototyping, and the way hardware emulation handles memories shows how different. Memories have evolved since Intel made semiconductor memory practical back in 1968. Until then, the leading technology was based on magnetic cores. Intel’s founders believed that semiconductor memory’s advantages –– smaller size, greater performance, reduced energy consumption –– would convince manufacturers to try the new technology. They were correct beyond their wildest expectations.
FPGA prototyping evolved from the ancient approach first introduced at the dawn of the electronic industry which consisted of building a prototype of a design under development using actual components. In a recent conversation with Dr. Wally Rhines, Mentor Graphics CEO, he told me he was involved in prototyping Texas Instruments’ first pocket calculator in the 1970s using a breadboard populated with TTL integrated circuits. He said the design team “emulated” the design.
FPGA’s reprogrammable nature simplified the prototyping task. Design teams did not have to build a new breadboard every time they had to validate a new design. Instead, all they had to do was to reprogram the FPGAs installed on a motherboard.
Today, a designer can build a prototype with one or several large FPGAs. When it comes to prototyping a memory system connected to the design under test (DUT), the typical approach is to install a memory chip on an extension board and plug that board on the FPGA prototyping motherboard.
Two advantages are inherent to this approach. Designers can install the actual memory device that will be connected to the taped-out design and be done with it. Second, they may run the prototype at a high speed, although not the real speed. The drawback is that the memory controller on the design cannot access the physical memory in a cycle-accurate way, which means the performance verification of the system is not accurate.
Emulation is a complementary verification technology. The emulator may use FPGAs, although not all emulators use them, but the deployment methodology is different.
Unlike an FPGA prototype, an emulator is an expensive resource that can serve a multitude of concurrent users and fit any design size. In an emulator, designers trade off the maximum speed of execution for fast setup time, automatic compilation, and 100% design visibility.
An emulator typically resides in a lab and is made available for remote access. Installing memory extension boards, though possible, would require the presence of personnel on-site and defeat the purpose.
Instead, a designer’s memory controller can be used without change inside the emulator because it is connected to an accurate model of the memory device. Memory devices are mapped into the emulator’s generic resources. Full visibility of the memory controller, device pins and contents are available using the emulator’s standard visibility and upload/download features. In addition, an alternative mode where the entire contents of the memory are in software on an external PC/Server maximize the memory size.
Instead of a catalog of memory extension boards, emulator vendors offer libraries of memory models.
As someone who’s been both a participant and an observer of the hardware emulation space, this announcement is just further indication of the great value these tools provide project teams under pressure to debug SoC designs.