Articles Authored by Lauro Rizzatti

Thomas Delaye, director of technical marketing in the Emulation Division at Mentor, a Siemens Business, recently studied how data could be used more effectively in chip design verification tools, such as hardware emulation.

Hardware emulation is a strategically essential ingredient of a verification flow used in a broad range of applications. It’s also an expensive line item in a yearly budget because of a variety of factors including acquisition cost and expenses to keep it operational, usable, safe and in good working condition.

When you want to improve or change a dish, the expert explained, you start with a basic, well-known recipe, and proceed to make small changes.

When it comes to using AI, look for problems that have rules. If there are rules that enable people to solve the problem, that helps a lot.

The problem with verifying today’s designs is that we have to deal with systems that are inherently unverifiable.

It just makes sense that we will find a lot of applications in which we can use the power of AI to improve our processes and build chips faster.

It just makes sense that we will find a lot of applications in which we can use the power of AI to improve our processes and build chips faster.

The first part of this article describes the advantages of the virtual mode over ICE. The second details a verification strategy, Veloce VirtuaLAB, built on top of the virtual mode. Three test cases will then show the benefits of Veloce VirtuaLAB.

In a recent talk on deep learning, BabbleLabs CEO Chris Rowen said, “I think of it as the construction of a complex numerical model that mimics the behavior of an even more complex but hidden system. The hidden system in question is often the brain.”

Silicon system design with deep learning has the same challenges with other complex system-on-chip-based designs, only more so.