Articles Authored by Lauro Rizzatti

Mipsology’s Zebra Deep Learning inference engine is designed to be fast, painless, and adaptable, outclassing CPU, GPU, and ASIC competitors.

A more efficient flow to support DSP development groups, such as VSORA’s, could help to ensure the success of 5G.

There are challenges unique to designing ASICs for networking applications. One is that bandwidth and latency performance tests for these devices require significantly more simulation cycles than required by other types of ICs.

Reading the transcriptions and watching the videos of these three talks delivers an exhilarating look at the semiconductor industry’s future.

This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.

Challenges facing chip design verification engineers are plentiful, but the opportunities, especially for AI applications, are abundant.

Siemens is buying Finland-based Sarokal. In this interview for VanillaPlus, Jean-Marie Brunet, senior director of Marketing at Mentor, a Siemens business tells Lauro Rizzatti, hardware emulation expert, at Rizzatti, LLC outlines the strategy behind the purchase.

Based on what attendees saw at DAC, the forecast for EDA could be cloud-based and changeable with heavy cloud cover but little rain and loads of potential.

A noteworthy piece of equipment is a hardware emulator whose COO is an interesting case for the range of parameters and criteria that contribute to its outcome.

Now, no obstacles stand in the way for any potential users to benefit from the power of emulation and meet their tape-out deadlines.