By preserving capacity without sacrificing coverage, verification engineering teams get comprehensive functional verification with minimal incremental effort and without a hit on emulation capacity. Source:  Electronic Design The huge undertaking of verifying a system-on-chip (SoC) design has challenged engineers for more than 20 years –– the amount of time spent on it hasn’t varied much … Read more

Source:  EDACafé With due differences in subject matter – classic opera versus chip design verification – and, in a judgement call, a trivial farce versus expensive and hard to use, I see a similarity with what’s happening with hardware emulation. First devised in the middle of the 1980s, driven by the progress in field programmable … Read more

Source:  EDACafé Many PBS stations in the U.S. are promoting the rebroadcast of the 1984 series “The Jewel of the Crown.” A jewel in the crown was my sentiment about the recent DVCon India, one of several design and verification conferences organized by the industry standards organization Accellera Systems Initiative. DVCon India was held in … Read more

An emulator’s performance — or its speed of execution — depends on the architecture of the emulation system and the type of deployment. Source: EETimes In my previous post, Performance in Hardware Emulators, I discussed the dependency of performance on the type of deployment. In this column, I will examine the relationship between emulation system architectures … Read more

One of the consequences of the IoT is an increase in the number of Ethernet ports. Source: Semiconductor Engineering The enormous growth of the Internet of things (IoT) has an enormous impact on network providers. After all, without the underlying network infrastructure, there would be no IoT. One consequence has been a significant increase in the … Read more

Source: Tech Design Forum Historically, the first method to be deployed and to this day most popular method for using a hardware emulator is the in-circuit-emulation (ICE) mode. In this mode, the emulator is plugged into a socket on the physical target system in place of a yet-to-be-built chip to support exercising and debugging the design-under-test … Read more

Emulation performance — or its speed of execution — depends on the architecture of the emulation system and the type of deployment. Source: EETimes Continuing my discourse on various aspects of hardware emulators (see also DAC Trip Report: Expanding EDA’s Charter & Topical Hardware Emulation), I now wish to discuss one of the most important aspects of … Read more

An Ethernet VirtuaLAB provides a software-controlled environment for generating, transmitting, and analyzing Ethernet packets to test Ethernet SoCs mapped inside an emulation platform. Source: Electronic Design With the spectacular surge in demand for connectivity, the Internet has become a major communications highway for billions of users. According to “Internet Live Stats,” the Internet reached out to … Read more

Source: ChipDesign In the not too distant past –– say 20- to 30 years ago –– hardware emulators were huge and hulking, with a massive amount of cables and wires trailing all over the floor. I still remember my first visit  to AMD in Austin, Texas, back in 1995, when I saw Quickturn’s Enterprise Emulation … Read more

Dr. Lauro Rizzatti paid close attention to trends at DAC two weeks ago and wrote them up in a trip report for EETimes readers. Source: EETimes As per tradition, Gary Smith kicked off the 52nd DAC June 7 in San Francisco, presenting his EDA industry forecast. Gary remarked that EDA is healthy at over $6 … Read more