With an expanding ecosystem to support hardware emulation coupled with a powerful new SoC verification solution, the prospects for the hardware emulation market look bright
Source: EETimes
Like many others in the semiconductor industry, I keep an eye on promising technology, which is how I came to track the progress of hardware emulation. It’s been a long slog, but an enterprising startup or two — along with the big three EDA companies — have managed to do the impossible. Hardware emulation today is a component of almost all verification flows for embedded system-on-chip (SoC) designs; it’s used for the toughest verification challenges, including hardware/software integration.
As the verification consultant Lauro Rizzatti pointed out in a blog post last month, the emulation market has grown to $350 million in annual revenue. Its growth has been driven by a variety of confluent factors. Of course, increased design complexity, compounded by the overwhelming presence of embedded software, tops the list, followed closely by verification engineers and project teams having a better understanding of the best applications for hardware emulation. It’s fair to note that these applications are increasing, too.
A shout out to the developers of the current crop of hardware emulators — they’re faster and easier to use. They’re mostly cost effective, as well. And, because their implementations have been enhanced dramatically, they offer better results. The marketing of hardware emulation has been stepped up, as well, and we’ve seen more industry focus and awareness on this market segment.
Most important, however, is the expansion of the deployment modes, from traditional in-circuit emulation to transaction-based verification supported by a growing ecosystem of tools and models, including speed adapters and verification IP.
Another prediction — this time from Gary Smith EDA (and cited by Rizzatti) — has the emulation market’s annual revenue growing to $1 billion by 2017, and this seems plausible. The market’s continued expansion will be due in large part to the ecosystem.
As hardware emulation goes mainstream, it’s only natural that more SoC verification software will become available to support these platforms and the project teams using them. In fact, the ecosystem recently expanded with the addition of promising technology to give verification engineers a way to generate test cases for use on hardware emulation platforms. This SoC verification technology eliminates the need to write hardware validation tests by hand, and it stresses all aspects of the chip before trying to boot the operating system and applications.
The current and universally accepted approach uses testbenches based on the Universal Verification Methodology (UVM) standard. That works for IP blocks and small subsystems, but it does not work for embedded processors. Verification engineers build a minimal full-chip testbench and wait until emulation or prototyping to run hardware/software co-verification. Since production software is not designed to find bugs in the chip design, a big hole remains in the thoroughness of verification. Some project teams try to fill this hole with handwritten tests, but these are difficult to write and expensive to maintain, and they address only the tip of the SoC verification iceberg.
The verification iceberg threatens to crater even the best verification strategy or hardware emulation platform. An automated approach to verifying shared and concurrent SoC resources, system and power management, application use cases, and performance has evolved from being a wish-list item to a must-have requirement.
The only way to verify an SoC effectively and efficiently is with fully automated test cases running on its embedded processors. These test cases are generated from graph-based scenario models that capture the intended behavior of a system. Since they are similar to traditional SoC data-flow diagrams, creating and maintaining scenario models is straightforward. They are portable and reusable throughout the scope of an SoC project and across multiple SoC projects. The first commercial implementation of this technology generates test cases across multiple platforms, from simulation and simulation acceleration to emulation, prototyping, and silicon validation in the bring-up lab.
With an expanding ecosystem to support hardware emulation coupled with a powerful new SoC verification solution, the hardware emulation market’s prospects look bright. We may well see it top $1 billion in revenue. The emulation watch goes back at least 20 years, but it’s satisfying to see it finally getting its due.
Thomas L. Anderson is vice president of marketing at the SoC verification firm Breker Verification Systems. He has more than a dozen years of experience in EDA verification applications and marketing, having served in increasingly responsible roles at Cadence, Synopsys, and 0-In Design Automation. Before moving into the EDA industry, he was vice president of engineering at Virtual Chips. He holds a bachelor of science degree in computer systems engineering from the University of Massachusetts at Amherst and a master of science degree in electrical engineering and computer science from the Massachusetts Institute of Technology (MIT).