The forthcoming Design Automation Conference (DAC) will be a prime venue to learn more about the varied uses of hardware emulation. Source: EETimes As much as I would like to take credit for the title of this viewpoint, I must step back and give credit to D.A. Davidson, a financial analyst firm that follows the Electronic … Read more
Source: EDA Café It wasn’t all that long ago when hardware emulation providers heading to DAC worked overtime to get their booths filled with interested verification engineers with big challenges. Hardware emulation was still viewed as an esoteric and expensive luxury that only few could afford. Fast forward to 2014. This year is prime time for … Read more
The fundamental difference between commercial FPGA-based emulators and emulators based on custom silicon lies in the core element that maps the design-under-test (DUT) Source: Electronic Design For more than 10 years, I was a vocal advocate of FPGA-based emulation systems and continued to tout their benefits through 2013.1 Since then, I’ve become a consultant with an expertise … Read more
With an expanding ecosystem to support hardware emulation coupled with a powerful new SoC verification solution, the prospects for the hardware emulation market look bright Source: EETimes Like many others in the semiconductor industry, I keep an eye on promising technology, which is how I came to track the progress of hardware emulation. It’s been a … Read more
Finding critical bugs in the interaction of the embedded software running with the underling hardware is like finding the proverbial needle in a haystack. Finding problems quickly in the course of running billions and trillions of cycles of operation requires unique hardware debug tools and a rigorous tracing methodology. Source: Electronic Design Propelled by the exploding demand … Read more
Source: Electronic Design While the quest for ever-increasing performance continues, it no longer does so at any cost—not since we slammed into the power wall. Power and performance now must be balanced, and numerous techniques have evolved for reducing power consumption at a given performance. Such techniques used to focus on circuit design only—by optimizing transistor sizes, … Read more
As the mainstream process node moves to 40 nm and as 28-nm, 20-nm, and 14-nm finFETs gain momentum, the largest designs are approaching billion-gate capacities. These trends make power-aware verification and switching activity tracking for power estimation extremely compute-intensive tasks that can only be addressed by the latest generations of emulators. Source: Electronic Design Designing a complex … Read more
Source: Electronic Design While the quest for ever-increasing performance continues, it no longer does so at any cost—not since we slammed into the power wall. Power and performance now must be balanced, and numerous techniques have evolved for reducing power consumption at a given performance. Such techniques used to focus on circuit design only—by optimizing transistor sizes, … Read more