Source: Evaluation Engineering Design for testability (DFT), a way to build testability into an integrated circuit (IC) at the design stage to lower testing costs and increase manufacturing yield, has been around for many years in several different forms. These methodologies—ad-hoc and structured—are able to effectively detect all faults in a circuit, reducing cost and time … Read more

Hardware emulation is widely considered the universal verification tool that can be used throughout the SoC development cycle Source: Electronic Design The Design Automation Conference — that veritable shopping bazaar for design automation tools — is fast approaching, and verification teams are starting to make their “must see” lists of vendors. Chief among them has to … Read more

Source: ChipDesign Several years ago, while at Automatic Test Equipment (ATE) leader Teradyne, I witnessed frequent debates on a fundamental dilemma: On the production/testing floor, is it better to pass a failing device or reject a good device? Obviously, both are bad choices. If you reject a good device, you shoot yourself in the foot since … Read more

Source: EDACafé The folks at DVCon have done a brilliant thing. They’ve invited Lauro Rizzatti to present at their upcoming conference on a topic that Rizzatti knows better than anybody, emulation. Last year alone, he wrote 40 articles on the subject. More importantly, of course, Rizzatti helped guide EVE, the high-flying European EDA company that led the field in emulation from their base in … Read more

Marrying high-performance hardware with “smart” applications will make emulators workhorses for addressing complex system-level design verification challenges Source: EETimes DVCon, a conference for design and verification engineers, kicks off next week in San Jose, California. At this conference, hardware emulation will be a much-discussed topic in the program and in hallway conversations. After three decades of … Read more

Source: Embedded Computing Design In today’s competitive landscape, getting complex electronic devices rich in embedded software to market faster while making them cheaper and more reliable is a very risky proposition. Not thoroughly testing hardware designs inexorably lead to respins, increasing design costs and lengthening delivery of the netlist to the layout process, and ultimately delaying … Read more

Source: EDACafé If I were to study the astrological charts for the week of February 29, I’d see many of the planets aligning around DVCon, the center of our verification universe. As always, it will be a special week chock full of topics related to verification. Tutorials, paper sessions, panels and exhibits should keep all attendees … Read more

A happy medium between in-circuit emulation (ICE) and a virtual environment with software-based test perhaps exists with Deterministic ICE Source: Electronic Design Admittedly, I have biases. For one, I’m partial to Italian food and the occasional Japanese sashimi. I’m also biased regarding the deployment modes of hardware emulation. I’m not fond of the in-circuit-emulation (ICE) mode, … Read more

Booting an OS such as Linux gets the designer to the starting line, but how does the real work commence for complex multicore designs destined for gaming, digital signage, and more? Source: Embedded Systems Engineering When software developers hear the word emulation, they often think software emulators and not hardware emulation. That’s changing, though, as the … Read more

Given the complexity of chip designs and the various verification stages along the way, project teams use both simulation and emulation in their verification flows Source: EETimes Simulators — for both analog and digital design — have been around for so long (~40 years now) that most project teams take them for granted. Hardware emulation has … Read more