Source: EDACafé If it’s February, that means the chip design verification community is gearing up for the annual DVCon. This year it will be held Monday, February 27, through Thursday, March 2. As always, it will be a jam-packed week full of tutorials, paper sessions and panels. And, of course, the Expo with 32 of … Read more
A hardware emulator provides enough power to keep the design for testability (DFT) verification schedule on track, increasing yields and ultimately boosting profits Source: Design News The development cycle of an integrated circuit (IC) –– or informally, chip –– from the conceptual stage to production and shipping to end-users involves several stages. One metric to measure … Read more
A virtual probe enhances hardware emulation’s appeal as data-center resource for hardware designers and software developers when it comes to verification. Source: Electronic Design Hardware emulation continues to prove itself as a handy tool for hardware/software co-verification and testing the integration of hardware and software. Booting an operating system and executing software applications takes billions … Read more
Source: Embedded Computing Design Chip design debug is a difficult discipline, and system-on-chip (SoC) design has made it more so. It’s like the proverbial needle in the haystack. For SoC designs it’s two haystacks, one for software, the other hardware. Software development groups often point a collective finger at the hardware group claiming it’s a … Read more
In an interview with Lauro Rizzatti, former CEO of EVE, Luc Burgun, explains how he crossed the bridge between hardware emulation and high-frequency trading. Source: EETimes In an interview with Lauro Rizzatti, former CEO of EVE, Luc Burgun, explains how he crossed the bridge between hardware emulation and high-frequency trading. It’s long been assumed that … Read more
Here are the answers to the five most common questions posed by chip designers and verification engineers to Dr. Lauro Rizzatti in 2016. Source: EETimes Here are the answers to the five most common questions posed by chip designers and verification engineers to Dr. Lauro Rizzatti in 2016. Business travel took me to several different continents … Read more
Source: EDACafé A hardware emulator provides enough power to keep the design for testability (DFT) verification schedule on track, increasing yields and ultimately boosting profits. Continuing a tradition started in the early days of the company, the European edition of the Mentor Graphics’ User Group meeting, now renamed User2User or U2U, was held Tuesday, October … Read more
Build testability into a custom chip during the design phase Source: Electronic Product Of all the electronic design automation (EDA) tools on the market, design for test (DFT) may be the most under-appreciated; even though building testability into a chip during the design phase will significantly lower hefty testing costs. According to recent analysis, the … Read more
Source: EDACafé The 2016 DVCon Europe was held in Munich, Germany, at the Holiday Inns City Center Hotel on October 19-20. This was the third year of the conference and it has a decidedly local focus. In its short life, DVCon Europe has become the leading European event for electronic industry participants, mainly chip and … Read more
By using the well-tested Gompertz function, semiconductor companies have a way to determine areas in which to focus their attention and investments. Source: EETimes Is there a way to predict the future of semiconductor revenue driven by new products? This was the provocative question Dr. Walden (Wally) Rhines, Chairman and CEO of Mentor Graphics, asked and … Read more