The problem with verifying today’s designs is that we have to deal with systems that are inherently unverifiable EEWeb By Lauro Rizzatti (Contributed Content) | Thursday, June 27, 2019 Jean-Marie Brunet, senior director of marketing at Mentor, a Siemens Business, served as moderator for a well-attended and lively DVCon U.S. panel discussion on the hot … Read more
It just makes sense that we will find a lot of applications where we can use the power of AI to improve our processes and build chips faster EEWeb By Lauro Rizzatti (Contributed Content) | Thursday, June 20, 2019 Jean-Marie Brunet, senior director of Marketing at Mentor, a Siemens Business, served as moderator for a … Read more
It just makes sense that we will find a lot of applications where we can use the power of AI to improve our processes and build chips faster EEWeb By Lauro Rizzatti (Contributed Content) | Thursday, June 13, 2019 Jean-Marie Brunet, senior director of Marketing at Mentor, a Siemens Business, served as moderator for a … Read more
Source: Part One: Tech Design Forum, Part Two: Tech Design Forum By Lauro Rizzatti and Gabriele Pulini | May 01, 2019 Part One Hardware emulation can be deployed in two modes. In-circuit-emulation (ICE): This consists of testing the design-under-test (DUT) with real traffic in a physical environment. Virtual mode: The DUT is here verified via a test … Read more
If DVCon U.S. is a bellwether or leading indicator, the chip design verification market and, more specifically, hardware emulation will be healthy for years to come. DVCon 2018, which took place earlier this year, was the place to be to discover the latest trends in chip design verification, much like it normally is. The who’s … Read more
With AI/ML chip designs containing between 5 billion and 10 billion gates, design verification using hardware emulation is the answer, although not all hardware emulators are the same Artificial intelligence/machine learning (AI/ML) is the ultimate hot topic of 2019, taking hold of chip design and the semiconductor industry’s imagination and not letting go — for … Read more
In a recent talk on deep learning, BabbleLabs CEO Chris Rowen said, “I think of it as the construction of a complex numerical model that mimics the behavior of an even more complex but hidden system. The hidden system in question is often the brain.” Source: ElectronicDesign Lauro Rizzatti | Feb 06, 2019 Deep learning is one … Read more
Silicon system design with deep learning has the same challenges with other complex system-on-chip-based designs, only more so Source: EEWeb By Lauro Rizzatti (Contributed Content) | Tuesday, January 22, 2019 In a recent presentation to a group of semiconductor industry executives, Chris Rowen, CEO and co-founder of BabbleLabs, stated that there are two important ways to look at … Read more
Changes to 2020 SSD controllers versus 2018 SSD controllers are comparable to the task of migrating from HDD controllers to SSD controllers Source: EEWeb By Lauro Rizzatti (Contributed Content) | Thursday, December 20, 2018 In the technology sector, occasionally a new requirement will drive a minor technical concern into a big issue. If not addressed properly and in … Read more
Combining these Apps with an emulation environment makes it possible to increase fault coverage, increase production yield, and reduce ATE test time and cost Source: ElectronicDesign Lauro Rizzatti | Dec 19, 2018 The design-for-test (DFT) technology was driven by the need to harness the runaway cost of testing silicon chips on the manufacturing floor. This phenomenon eventually … Read more