If DVCon U.S. is a bellwether or leading indicator, the chip design verification market and, more specifically, hardware emulation will be healthy for years to come.
DVCon 2018, which took place earlier this year, was the place to be to discover the latest trends in chip design verification, much like it normally is. The who’s who of verification passed through the doorways of the DoubleTree Hotel in San Jose, California, all eager to learn what’s new and compare notes on best practices.
While AI chips are a hot topic, determining how to apply AI or ML to improve the verification methodology in design tools and technology is an unmistakable trend. One attendee noted that it’s an area of expansion in which AI can help analyze the massive amount of data generated by hardware emulation to verify large designs. What to look for and where to focus on in those terabytes of data is frustrating, time-consuming, and a real challenge. He believes that AI embedded into verification tools will help target a verification engineer’s approach.
Trending verification topics didn’t stop with AI/ML. Another emerging trend and the topic of an early-morning panel discussion was balancing verification with RISC-V ISA compliance. One panelist suggested that RISC-V introduces new verification challenges. In particular, he noted that thoroughly testing a modern processor like an Arm CPU requires several petacycles (where peta refers to quadrillion, or 1015). For comprehensively testing an extendable, open-instruction set such as RISC-V’s, the number of verification cycles swells by at least one order of magnitude.
Another attendee noted that bug-hunting will not ensure RISC-V ISA compliance when ISA customization and implementation optimization lead to additional challenges with regard to reliability, compliance, and economics.
Verification of the entire hardware/software ecosystem, not just the hardware design, is not new to a verification engineer’s wish list. However, it recently moved from “wish list” to “must have.” Consensus is building for a more abstract level of debugging and a systemic workflow. Both are good signs for the further adoption of hardware emulation.
The crystal balls came out in more than one presentation and hallway discussion. Several attendees predict more custom chips and domain-specific chips paired with domain-specific languages. Still others expect fewer opportunities to rely on common standards and common programs. While design tool providers build common solutions, more internal proprietary designs, standards, and tools will be forthcoming.
One last intriguing prediction is about the semiconductor business in general. Companies such as Facebook, Amazon, Apple, Netflix, and Google — otherwise known in the financial markets as FAANG tech stocks — or a non-startup newcomer could emerge within the top 10 semiconductor makers within the next few years. These companies are already building chips, and they all need robust verification tools such as hardware emulation now and in the future.
If DVCon U.S. is a bellwether or leading indicator, the chip design verification market and, more specifically, hardware emulation will be healthy for years to come.