Lauro Rizzatti Source: EDACafe Many of you are probably familiar with Lauro Rizzatti, who has written countless articles on the value of emulation for verifying system-on-chip (SoC) designs and been an occasional guest blogger here on The Breker Trekker. Lauro recently published an article in Electronic Engineering Times that really caught our attention. We could not possibly agree more with … Read more
Verification Consultant Lauro Rizzatti explains that the three different types of hardware emulator offer different design capacities, thereby giving users more options Source: EE Times Unlike software simulators, whose specifications do not mention limits in design capacity, a primary specification of hardware emulators is the maximum size of the designs they can handle. More to the … Read more
Hardware emulators are versatile and can verify designs with full visibility for thorough debugging. Source: Electronic Design Engineers often turn to two tools to verify their complex SoC designs: hardware emulation and FPGA prototyping. Some verification teams will use one over the other, while other teams remain confused about their differences and are looking for answers. Electronic Design … Read more
Verification consultant Lauro Rizzatti says that if he’s correct in assuming Apple’s using hardware emulation in its verification flow, the iPhone 6 should be completely debugged and working perfectly. Source: EETimes While driving down University Avenue in Palo Alto one sunny morning recently, I caught a glimpse of an incongruous sight: a line of well-dressed professionals … Read more
Source: Chip Design Hardware Emulation: The Ultimate Weed Whacker (PDF)
Source: Tech Design Forum It’s budget season. Annual reviews are well under way at many departments within semiconductor companies. It’s something most managers dread, a marathon of meetings spent justifying expediture and enduring possible cuts. Even though engineering departments do not budget entirely on a yearly cycle – most spending is determined by project cycles – … Read more
Design and verification project groups have a new tool in the arsenal that will enable better hardware emulation results, greater efficiency, and increased productivity Source: EETimes More than once, I have heard design and verification project groups complain about the lack of a unified and consistent SoC (system-on-chip) verification process. Almost all of them were juggling … Read more
Greater time-to-market pressures, along with escalating hardware/software integration and quality concerns, make the verification process a strategically important step in chip design. Coming to the rescue is a new generation of cost-effective hardware emulators Source: Electronic Design Typical performance is approximately 2 MHz on a 10-million-gate design and a top speed of 1 MHz on 100-million-gate … Read more
Source: Electronics360 Almost three decades ago, management consulting firm McKinsey and Co. postulated that a late market entry in highly competitive markets with short market windows has devastating effects on profits. Applying this wisdom to the semiconductor industry where almost all markets are highly competitive, three factors contribute to disastrous results, including engineering cost overruns, respin costs … Read more
Lauro Rizzatti implores designers to follow the crowd, defying moms everywhere Source: EETimes When you were a kid, your mother may have admonished you when you wanted to do something everyone else was doing by saying: “Just because someone else does something, doesn’t mean you should.” Well, I hate to disagree with mom, but project teams … Read more