By Lauro Rizzatti (Contributed Content) | Monday, August 20, 2018
Challenges facing chip design verification engineers are plentiful, but the opportunities, especially for AI applications, are abundant
It’s an exciting time for anyone in the chip and electronic design automation (EDA) industry, asserts Dr. Raik Brinkmann, president and CEO of formal verification provider OneSpin. Dr. Brinkmann uses new computer architectures, breaking the Von Neuman principle and pushing computing to a different level as an example, and says that they offer an opportunity for agile EDA companies with significant technology portfolios.
Artificial intelligence (AI), however, captures Dr. Brinkmann’s imagination, and he is studying what it can do to help design and verify chips. Implementing AI applications on hardware, he begins, involves mapping algorithms developed for AI into a hardware platform that could be an ASIC, an FPGA, a DSP, or one that’s more sophisticated. Each has a verification challenge: verifying the algorithm.
Once engineers have decided on a platform and architecture, they usually trust the implementation flow and platform, though sometimes a more rigorous approach is required, such as targeting safety-relevant applications through AI algorithms. They may use specific verification techniques for the algorithm itself. The challenge is to pick the right platform for the application.
An AI platform consists of a general-purpose processor that is used to manage the data and administer all of the types of computation that it needs to perform. Some accelerators are specific to an application; others can be more generic and support a variety of applications. A memory subsystem and a set of input/outputs (I/Os) to move data in and out complete the AI platform. These platforms need to be robust and may provide some safety guarantee, especially in the automotive space. Most of the established processor companies, as well as FPGA companies and cloud computing companies, are working on these types of architectures and platforms in order to accelerate their computations.
Accelerating AI holds enormous promise. More than 80 startups are working on AI accelerators, marvels Dr. Brinkmann, and this is an interesting and large space to be involved in right now. In the automotive space, engineers are considering centralized computerized platforms with high memory bandwidth and high-speed interconnect within the system to allow for more flexibility and lower cost overhead.
For the most part, the main criterion driving the selection of the platform for AI applications is the trade-off between performance and flexibility. FPGAs and ASICs are rigid in the types of architecture they can support for AI applications. While they offer better performance and throughput, lower latency, less power, and higher accuracy, they are inflexible, making it hard to map general algorithms to those architectures.
Building general algorithms and changing the architecture of the algorithms complicates the design process. The challenge is to have a highly automated flow to map the algorithms to the hardware platform. This is easier with CPUs, GPUs, and DSPs but harder for FPGAs and even more so for accelerators. In general, it is hard to achieve processing power and flexibility through a single approach.
Xilinx is developing a new adaptive computing platform with an FPGA-based device that is a combination of FPGAs with sophisticated DSPs plus distributed memory targeting C++ and Python programmers. At the same time, Xilinx is trying to make the FPGA more flexible and easier to target different algorithms, but there are limitations. Xilinx is attempting to make the architecture more flexible. Xilinx’s efforts to achieve both goals must be tested.
Another example could be massive parallel processing. This takes the general-purpose computing approach to make it more scalable. For example, Kalray recently released a processor chip with 288 cores targeting AI applications as well as data centers.
Both examples belong to the heterogeneous category for reconfigurable or adaptive computing, in which general-purpose computing is combined with programmable accelerators. This is a recent trend with a similar problem — complex designs that are difficult to verify.
While different verification engines are used today to verify complex designs, they generally are not adequate for verifying AI designs because there are too many different architectures to be explored by the engineers of such systems. A mandatory requirement calls for fast and scalable design and verification environments that are able to manage multiple levels of verification without capacity limitations in the automation process.
An example is the block-level verification of building blocks such as a DSP with multiply/accumulate units and verifying the aggregation of these blocks. Smaller blocks are combined into massive chips, which are a huge investment for companies developing them. A company with a 7-nanometer design can’t risk problems at the system-on-chip (SoC) level. To alleviate any issues, a rigorous verification process must be in place at both the block level and the SoC level.
Other application challenges include autonomous driving, wherein engineers must consider functional safety. This is a verification challenge inherent in the technology, all compounded by the need to perform the whole functional safety verification within the project’s budget and timeframe.
Standard verification technology may be applicable for block-level verification, although it needs a higher degree of automation and confidence. This is also where formal verification can add value.
In a paper at DVCon Europe 2016, Bosch described how it automatically created a DSP from the instruction set architecture (ISA) and then verified it through a formal tool using generated assertions, where even the assertion set itself was tested for gaps and confidence in the specs. This allowed Bosch to design and verify at the ISA level and automate a great deal of work, thereby accelerating the design process.
Another example is the floating-point units (FPUs) that support fast multiply/accumulate or fused multiply/accumulate (FMAC) that are at the heart of many AI implementations. Most of the algorithms used in neural networks today are based on many operations that use multiplication and addition on floating point values, which subsequently need to be scaled to different sizes and for different needs. This creates a big verification problem that is addressed by automatically verifying the implementation against the IEEE floating-point standard. As detailed in a recent DVCon paper, Xilinx used formal verification IP and an app to perform this verification, an example whereby scalability and performance of the design flow comes from the automation and the ability of formal to prove complex assertions.
Massively sized designs at the aggregate and the SoC levels are where traditional verification approaches break down. Current tools are not fit for the purpose, and this is the challenge that EDA must address. It is not just the size of the design that requires a huge capacity to verify connections between modules and module instances on a 10-billion gate design, but also human capacity is hitting a limit. The effort to specify tens of thousands of modules and millions of instances with deep hierarchies is a tedious and error-prone approach. Both the tools and the manual effort are a big challenge, so new approaches are necessary — this is something that EDA companies can work on and help to solve.
As Dr. Brinkmann points out, challenges facing chip design verification engineers are plentiful, but the opportunities, especially for AI applications, are abundant. He’s right — this is a great time to be in the chip design and EDA industries!