A Winning Formula

Verification ExpertDVCon attendance could rival Super Tuesday with hardware emulation ROI draw

Source: Semiconductor Engineering

It may be fitting that DVCon will be held the same week as Super Tuesday this year, the day when the greatest number of states in the U.S. hold primary elections. Big dollar expenditures and return on investment (ROI) strategies are part of today’s political landscape, as they are with chip design and verification.

Missing a delivery window for an electronics device can cost 25% or more of the potential revenue or be the ruin of a semiconductor company. That’s why so many semiconductor companies that have become highly risk averse are turning to hardware emulation, an EDA tool with high value and even higher ROI.

Here’s why. Unique in the EDA space, hardware emulators are powerful, undaunted by design sizes, and they can be deployed in several operational modes addressing a variety of verification objectives. No other design verification tool can cover such a wide territory. They’re also much easier to use than previous generations, and their cost per verification cycle is the lowest in the industry. They can map any design size, even those with more than 1 billion gates, with a setup time measured in a day or a few days. They can verify designs up to six orders of magnitude faster than RTL simulators and give users full design visibility for thorough debugging.

Hardware emulation is a versatile and universal verification tool used across the entire SoC development cycle for thoroughly testing the functionality of an increasingly complex design and validating its embedded software. As a result, hardware engineers and software developers share the same system and design representations because it offers combined hardware and software views of the design. They can work together to debug hardware and software interactions, tracking a bug across embedded software and the hardware.

Emulation has moved out of the single-user mode into the datacenter, offering remote access, support for several or as many as one hundred concurrent users. This capability can handle multiple large-capacity designs or any combination of small and large designs, strengthening its ROI. As well, a centralized team of emulation experts can assist many more users dispersed in separate geographies over different time zones.

Further decreasing risk is hardware emulation’s reliability and performance. Hardware emulation can eliminate costly respins, a huge advantage when the average respin cost exceeds $10 million at 28nm. While hardware emulation isn’t an inexpensive verification tool, it could save millions of dollars if it were to find a bug ahead of tape out. Otherwise, it’s a silicon respin. With design costs escalating, here’s a surefire way to contain costs and see a tangible ROI.

Of course, hardware emulation would be considered a capital expense and the purchase decision would travel up to senior management for signoff, perhaps eating into the time-to-market window. Justifying the purchase shouldn’t be too difficult, however. When the budget analysts do an assessment, they should find that hardware emulation is well worth its value and pricing is about a penny per gate.

Armed with this new appreciation for hardware emulation, DVCon attendee numbers could rival Super Tuesday’s turnout. The DVCon program includes a session titled, “Effective Emulation,” and a panel, “Emulation + Static Verification Will Replace Simulation.” Both should offer added insights into hardware emulation’s ROI for risk-averse project teams.

Don’t forget to vote!