Finding a Bug in the SoC Haystack

Finding critical bugs in the interaction of the embedded software running with the underling hardware is like finding the proverbial needle in a haystack. Finding problems quickly in the course of running billions and trillions of cycles of operation requires unique hardware debug tools and a rigorous tracing methodology. Source: Electronic Design Propelled by the exploding demand … Read more

Four Technologies Converge in Hardware Emulation

Source: Electronic Design While the quest for ever-increasing performance continues, it no longer does so at any cost—not since we slammed into the power wall. Power and performance now must be balanced, and numerous techniques have evolved for reducing power consumption at a given performance. Such techniques used to focus on circuit design only—by optimizing transistor sizes, … Read more

Power Trumps Performance In Today’s SoC Designs

As the mainstream process node moves to 40 nm and as 28-nm, 20-nm, and 14-nm finFETs gain momentum, the largest designs are approaching billion-gate capacities. These trends make power-aware verification and switching activity tracking for power estimation extremely compute-intensive tasks that can only be addressed by the latest generations of emulators. Source: Electronic Design Designing a complex … Read more

Power Islands Need Power-Aware Emulation

Source: Electronic Design While the quest for ever-increasing performance continues, it no longer does so at any cost—not since we slammed into the power wall. Power and performance now must be balanced, and numerous techniques have evolved for reducing power consumption at a given performance. Such techniques used to focus on circuit design only—by optimizing transistor sizes, … Read more