Hardware emulation future is exciting
- May 23, 2020
- Posted by: Lauro Rizzatti
- Category: 2020
By Lauro Rizzatti, Verification Expert
The future of hardware emulation has been proclaimed impressive, as shown by its upward market performance trend. As revealed by a recent ESD Alliance Market Statistics Service (MSS) report, the total revenue in 2019 stood at over $10 billion, representing an 8.3 percent increase over 2018 performance. The hardware-assisted verification, inclusive of hardware emulation and field programmable gate array (FPGA) prototyping, also reported a revenue of $650 million in 2019, compared with $549 in 2018.
With this 55 percent increase, the latest MSS report has enlarged the confidence that, the trend will likely continue for years to come. Further enhancing this assurance, is the ability of in alternative to in-circuit-emulation (ICE) mode, which allows an emulator to be accessed remotely in virtual mode, removing the need to operate speed-adapters in labs. A big plus in the COVID-19 Corona Virus era.
While the ESD Alliance’s MSS does not offer a more granular look at the revenue of the two, emulation revenue is higher, possibly in the ballpark of 80 percent. This is based on financial reports from the three vendors. Remarkably, the category surpassed register transfer level (RTL) simulation revenue, an historical event and a possible topic of a future blog post.
The differences between the two verification approaches may explain the wide disparity in revenue. From a 40,000-foot perspective, hardware emulation targets pre-silicon verification of system-on-chip (SoC) designs with hardware debugging, system validation, and hardware or software integration, including debugging, design errors propagating across the hardware or software domains.
FPGA prototyping focuses on embedded software validation and system validation. Prototypes can also act as demo platforms for early samples of new products. Emulation requires powerful debugging capabilities, fast compilation, and swift execution, in the 1-3MHz. FPGA prototyping trades off debugging capabilities and compilation speed for faster execution, over a wide range from a few to more than 100 megahertz and heavily dependent of design sizes.
Hardware emulation also outshines any other verification tool with an impressive variety of use models, for a multitude of verification tasks, and virtually limitless applications.
It accelerates the universal verification methodology (UVM), verifies a design under test (DUT) via software stacks including drivers, an operating system, and important applications. It performs low-power verification based on several power standards, generates a design activity database for peak and average power estimation tools, and accelerates design-for-test (DFT) analysis. In addition, verification coverage, assertions, performance analysis are all supported by hardware emulation.
In summary, emulation can accelerate design verification of any design, irrespective of type and size. Welcome news for leading-edge segments of the electronic industry creating designs for 5G, Artificial Intelligence (AI) or Machine Learning (ML) AI/ML and autonomous driving vehicle applications that typically excel in dimensions and complexity.
All these are accomplished regardless of the underlying emulation architecture. In fact, the three emulation suppliers chose three rather different architectures that possess unique sets of advantages and drawbacks. And, the growing need for hardware emulation, stimulates the three vendors to regularly design even more powerful versions of their platforms.
Most verification engineers agree that hardware emulation is essential for improving verification productivity for accelerating time-to-market delivery, achieving better product quality. In fact, a return-on-investment (ROI) analysis proves that the tool acquisition and operational costs pale vis-à-vis the savings from meeting the verification schedule and reducing or eliminating silicon re-spins. No doubt, emulation is a key component of any verification strategy.