DVCon US: Machine Learning Lands in EDA
- March 13, 2017
- Posted by: Lauro Rizzatti
- Category: 2017
Each DVCon event tends to have a common thread throughout the keynote presentations, panels, sponsored lunches, tutorial and technical sessions. I would pick “machine learning” as the new EDA frontier for DVCon US 2017, held in San Jose, Calif., at the DoubleTree Hotel February 27-March 2. In the keynote and panels machine learning was mentioned here and there as the panacea to achieve full automation of the verification process.
Attended by approximately 1,051 badge holders (exhibit-only, technical conference and booth staff), it encompassed nine tutorials, 12 sessions with a total of 39 technical papers and 19 posters, and 31 exhibits.
Presenters debated diverse facets of design verification:
- Portable stimulus –– one tutorial with seven speakers, one session with three papers, one poster, one panel
- Formal analysis –– two tutorials with eight speakers in total, two session with seven papers, and four posters
- Universal Verification Methodology (UVM) –– one tutorial with five speakers, three sessions with nine papers in total), low-power design (one tutorial with five speakers, one session with three papers, and two posters
- Design verification languages –– one tutorial with two speakers, two sessions with sever speakers in total, and one poster
A few more tutorials, sessions and posters debated design verification, in general, including coverage, testbench automation, SoC verification, IP verification, design safety verification and analog/mix-signal verification.
Hardware emulation, my favorite topic, was mentioned in the keynote, but it was the subject of only one paper delivered by Samsung in the Power Optimization session.
The keynote presentation, titled “Tomorrow’s Verification Today” was delivered by Dr. Anirudh Devgan, Sr. VP and GM of the Digital & Signoff Group and System & Verification Group at Cadence. In the opening remarks Dr. Devgan reminded the audience that it was Mardi Gras, and went on to discuss the trends in design verification. His unique position overlooking the entire design verification landscape served by a major EDA player gave him the perspective to review the limitations in today’s tools, and to appraise the requirements to address tomorrow’s hardware and software development needs.
Regarding formal analysis, Dr. Devgan said that formal verification has made lots of progress over the years, but there is room for improvement. Three areas need attention:
- Expand dramatically the capacity of the tool
- Improve the ease of use of the tool
- Assure the interplay of formal with simulation.
A Special Session hosted by Harry Foster, chief technologist at Mentor Graphics presented the summary of the 2016 Industry Survey of the functional verification landscape. The 2016 survey continued on the footsteps of the previous 2007, 2009, 2012, 2014 surveys. The 2014 and 2016 surveys, conducted on a worldwide basis in a double-blind study covering all electronic industry market segments were never published.
The presentation included a trove of interesting data. Given my personal interest in hardware emulation, I wish to mention that the study showed that today, 24% of the projects adopted emulation. Between 2014 and 2016, there was a significant increase in the use of emulation for IP development and verification. The following chart maps various objectives for adopting emulation.
DVCon US also included three panels, and four sponsored lunches by each of the three EDA giants and Accellera.
In one of the panels titled “The Verify Seven” and backed by the ESD Alliance, OneSpin Solutions and Vista Ventures’ Jim Hogan, six prominent representatives from small EDA companies debated the pains and joys of starting a company. Presenters included:
- Andy Stein, VP of sale, Avery Design Systems
- Rick Carlson, VP of Worldwide Sales, Verific Design Automation
- Raik Brinkmann, President & CEO, OneSpin Solutions
- Prakash Narain, President & CEO, Real Intent
- Adnan Hamid, CEO, Breker Verification Systems
- Phil Moorby, Chief Architect, Montana Design.
All shared similar experiences. They spent years and dollars trying different alternatives before settling on a definite product and a business model. My recommendation to a potential entrepreneur is to think long and deep what to do before jumping into it. It would save time, money and, mostly, frustration.
Phil Moorby, credited as the father of Verilog, participated in two other panels and in all three stated that the SystemVerilog language, while the pinnacle for design description, is a rather poor choice for testbench description. Inadequate for parallelization, it is rather inefficient when processed by x86 or GPU architectures. A better choice, said Phil, would be a C/C++ approach. More than one attendee wondered what was cooking at Montana, but Phil kept his lips sealed.
In a panel titled “Users Talk Back on Portable Stimulus”, organized by Nanette Collins, founder of NVC Marketing and Public Relations, and moderated by Adnan Hamid, CEO of Breaker Verification System, the five panelists, including Asad Khan, Cavium, Dave Brownell, Analog Devices, Mark Glasser, nVidia, Wolfgang Roesner, IBM, and Sanjay Gupta, Qualcomm, debated the status of the portable stimulus initiative. All five agreed that looked from 30,000 feet, the initiative is welcome and badly needed. But as they moved down to the details of the proposed plans disagreement, contradiction, and a bit of confusion arose. It will be interesting to observe the evolution of the proposal.
All considered, the 2017 DVCon US conference was successful, but I cannot withhold my disappointment for the virtual absence of the topic of hardware emulation, especially when compared to the exposure of formal analysis. Just consider that via the deployment in virtual mode, an alternative to in-circuit emulation (ICE), and the adoption of emulation Apps to perform a variety of functional verification tasks, hardware emulation is used across the verification landscape, and its “shift-left” adoption continues to progress. When installed in a data center, it can serve a worldwide design verification community 24/7 all year round, optimizing the return-on-investment. All market segments from processor to networking, storage, multi-media, automotive and more, benefit from the use of emulation. In fact, without emulation, functional verification of the monstrous chip designs the industry is cranking out today would not be possible.