February Means DVCon is Coming!
- February 6, 2017
- Posted by: Lauro Rizzatti
- Category: 2017
If it’s February, that means the chip design verification community is gearing up for the annual DVCon. This year it will be held Monday, February 27, through Thursday, March 2. As always, it will be a jam-packed week full of tutorials, paper sessions and panels. And, of course, the Expo with 32 of the leading verification companies showcasing their tools will be a highlight.
The stage will be set Monday by conference sponsor and host Accellera with three standards-related tutorials on portable stimulus, universal verification methodology (UVM) and SystemC. An Accellera lunch will update attendees on working groups and an outlook for the future. The lunch will include an awards ceremony as well.
Capping Monday’s activities will be the popular Booth Crawl in the expo area from 5 p.m. until 7 p.m.
Tuesday will begin with the opening session, followed by seven sessions throughout the day. Not to be missed will be a special session with Mentor Graphics’ Harry Foster titled, “Trends in Functional Verification: A 2016 Industry Study.” Harry will report on the findings from the 2016 functional verification study and provide insights into the state of today’s electronics.
Other sessions Tuesday will address a range of topics, such as UVM, coverage, verification and power optimization, and SystemVerilog. A Cadence-sponsored lunch on application-specific verification will be followed by the keynote, “Tomorrow’s Verification Today,” by Anirudh Devgan, Cadence’s Senior Vice President and General Manager of the Digital & Signoff Group and System & Verification Group.
A poster session will be from 10:30 a.m. until noon, and the exhibit floor will be open from 2:30 p.m. until 6 p.m.
Wednesday’s program will offer two panels on portable stimulus and SystemVerilog at 8:30 a.m. and 1:30 p.m., respectively. Six sessions throughout the day will cover formal verification, analog mixed-signal and verification reuse and debug. A Synopsys-sponsored lunch will explore verification using Synopsys tools.
Like Tuesday, the exhibitor floor will be open Wednesday from 2:30 p.m. until 6 p.m.
I’m hearing talk of a few evening activities hosted by DVCon exhibitors on both nights. More details should be forthcoming.
Thursday is a continuation of the tutorial program with six sponsored tutorials, two each from Cadence, Mentor and Synopsys. A Mentor Graphics-hosted lunch on an enterprise verification platform will be presented by Harry Foster and Steve Bailey.
While the program looks well balanced and appealing, I recommend that the Steering and Program committees make it a point to add at least on hardware emulation session to next year’s program. Only one session Wednesday includes an emulation paper on hybrid emulation, an unfortunate oversight.
Make no mistake. Hardware emulation adoption is a big trend and a quiet but unstoppable revolution has started in chip design verification. Exhibitors think so, too.
I’m looking forward to DVCon this year and hope to see you there! Please say hello and introduce yourself.