Much Less Efforting Required
- August 25, 2016
- Posted by: Lauro Rizzatti
- Category: 2016
I had a chat with a friend yesterday who announced: “Less efforting is working for me.” The use of the noun effort as a verb –– efforting –– didn’t send me to my online dictionary to check my grammar or linguistic skills. Instead, it took me back 30-odd years to the early days of hardware emulation when efforting could have been the catchphrase.
In those days from the 1980s, the emulator arrived with a crew of applications engineers (AEs in a box, we used to say). Even they didn’t have a magic touch –– it seemingly took forever to tweak the system just so to get it to work. Pricing required some justification efforting as well because they were expense verification tools. As a result, they were reserved for only the largest and most complex chip designs, which, in those days average about 100,000 ASIC gates. Big price tag, big chips, lots of efforting.
Efforting continued into the 1990s as hardware emulation became a bit more popular, though they were an unsightly mess with cables snaking around the boxes, like spaghetti enveloping meatballs, so much so that they were relegated to a back room. With all those cables came in circuit emulation (ICE), the default, actually the only use model to verify the design-under-test (DUT) with real traffic data. While effective, the data in and out of the emulator ran at a lower speed than the actual speed of the real traffic data, requiring the insertion of speed adapters and additional efforting. Further, the manned supervision commanded by the ICE mode limited hardware emulation’s ability to become a shared remote resource.
About 20 years ago, spearheaded by a tiny French startup by the name of Meta Systems, emulators with custom chips were introduced. They offered a better and more transparent way to map a design, provided total visibility into the design, mandatory for effective debug that led to the acceleration mode driven by software testbenches. This meant less efforting for verification engineers because acceleration mode advanced to become a virtual mode made possible by the transaction-based communication between the emulator and the testbench running on the workstation.
Here we are today. Much has changed and much less efforting is required to deploy hardware emulation, even as designs reach one-billion gates or more, include multicore processors and embedded software. Use models are growing, the latest being Deterministic ICE, removing a final weakness with ICE. Because real-world traffic is not repeatable and non-deterministic, the efforting to debug chip design is time-consuming. Deterministic ICE replaces a physical ICE environment with an equivalent virtual environment, giving designers a way to check assertion and coverage closure, perform low-power analysis and power estimation and resume embedded software debugging.
In virtue of enormous design capacity, remote access and multi-user capabilities warrants that the emulator can become a datacenter resource, enabling worldwide project teams access at anytime from anywhere.
Turning nouns into verbs is a popular trend these days. Another popular trend is the growing adoption of hardware emulation in the verification flow that will continue for the foreseeable future, ensuring far less efforting for verification engineers.