Power Analysis has a New Look
- June 22, 2015
- Posted by: Lauro Rizzatti
- Category: 2015
Power continues to be a primary concern for handheld and smart devices, with their high resolution screens that require long battery life, as well as for wall-plugged equipment in datacenters and network configurations, for which the cost of operation is a key market factor. While FinFET process technology reduces static leakage, dynamic power remains a challenge.
However, a new usage model for handheld and smart devices is driving a methodology shift in the way power is analyzed. Complex system-on-chip (SoC) designs are now verified using live applications that require booting the operating system and running software applications on an emulator. In this verification model, it is more effective to use the power switching activity plot, which is generated during emulation, to pass real-time switching activity information to power analysis tools where potential power issues can be evaluated.
When designs with significant software content are run on an emulator, the existing method of generating activity data creates waveform viewer files (like FSDB) that are too large for power analysis tools to handle in any practical manner. Generating an activity plot of a 100 million gate design for 75 million design clock cycles typically takes a week or more.
To accommodate the emerging new verification model, tools like Mentor’s Veloce Power Application replace the file-based power analysis flow with dynamic-read waveform API integration to power analysis tools. This dynamic-read waveform API approach captures the information from the power switching activity plot and transfers that data to power analysis tools. All operations run in tandem, from emulating the SoC, to capturing the switching data, to the reading of the switching data by the power analysis tool, to the generation of the power numbers. This new power analysis process enables accurate power calculation at the system level, better power exploration at the register-transfer level (RTL) for power budgeting and tradeoffs, as well as more accurate power analysis and sign-off at the gate level.
With this new approach, the typical process of running the emulator, creating the file, reading the file into the power analysis tool, and then running the power analysis tool is now reduced to the emulator and power analysis runtimes. Design teams no longer have giant files to deal with, which means no more wasted space, and no more lost days in file creation and file loading. In turn, that means design and verification teams can start RTL power exploration very early in the design cycle. They can perform power tradeoffs and architectural adjustments further upstream than ever before, and then continue to use the same process after RTL is synthesized into a gate-level representation. At the gate level, they can attain more accurate power measurements and perform additional fine tuning before tapeout, and then finish with power signoff in a targeted application environment.
This new approach provides a fast, clean, and highly effective method to quickly and thoroughly estimate power consumption of a modern SoC design. The efficiency of capturing real power consumption during emulation and passing that information to power analysis tools provides significant improvements in power analysis runtime and performance that can help ensure designs achieve their power and performance goals in a reasonable time.